With the advance of the integrated circuits technology into the ultra large scale integrated circuits (ULSI), the sizes of various devices have gotten smaller and smaller and the design rules of the various devices tend to build the three dimensional structures rather than the plane structures of conventional technique on the semiconductor substrate, in order to manufacture the devices and the integrated circuits with required high integration. Thus, except the shrinkage of the areas which the devices occupied is obtained, the operation performance of the devices are also controlled precisely. Wherein for the trench power metal-oxide semiconductor transistor devices, the space required to manufacture the whole transistor structure is decreased substantially due to the gate structure of the transistor is formed in the trench on the substrate and the source/drain structures are formed above/underneath the gate structure respectively. Thus, the trench power MOS transistor is widely applied and developed in semiconductor manufacture.
Please refer to FIG. 1, wherein the trench power MOS transistor formed by the prior process is illustrated. First, a semiconductor substrate 2 is provided, then the pad oxide layer 4 and nitride layer 6 are deposited on the substrate 2 in sequence. The trench pattern are then defined on the oxide layer 4 and the nitride layer 6 by using the well known photolithography. Next, the nitride layer 6 is used to serve as an etching mask for etching the substrate 2 to form the trench structures 8 on the substrate 2.
After the trench structure 8 is formed, as shown in FIG. 2, a thermal oxidization procedure is done for the substrate 2 to form the thin gate oxide film 10 on the outer surfaces of the trench structure 8. Then, a doped polysilicon layer 12 is formed on the substrate 2 and filled into the trench structure 8. Next, the etching back step is performed to etch the doped polysilicon layer 12 above the nitride layer 6 and to make the doped polysilicon layer 12 have the recessed surfaces as shown in FIG. 2. The top surface of the doped polysilicon layer 12 is lower than the pad oxide layer 4 in order to facilitate manufacturing the field oxide separators in latter process. Then, an implant step is performed to form the doped areas 14 for serving as the source structures of the transistor manufactured in latter process underneath the pad oxide layer 4 and adjacent to the gate oxide layer 10 in the substrate 2. Namely, the source areas 14 are formed adjacent to the sidewalls of the trench structure 8. It is noted that the substrate 2 is used to serve as the drain structure of the trench power MOS transistor.
Next, refer to FIG. 3, a thermal oxidization process is performed for the substrate 2 to form the field oxide layer 16 on the top surface of the doped polysilicon layer 12 for being the insulator structure. In general, the field oxide layer 16 has a thickness about 2500 angstroms in order to promote the insulating efficiency. Besides, the thickness of the field oxide layer 16 is controlled precisely by elongating the process time of the thermal oxidization procedure.
However, the encroachment areas A, as illustrated in FIG. 3, occur along the junction between the pad oxide layer 4 and the gate oxide layer 10 during forming the field oxide layer 16. Namely, the field oxide layer 16 extends through the slits between the pad oxide layer 6 and the gate oxide layer 10 and into the substrate 2 to form the encroachment areas A in the doped areas 14. Thus, the profiles of the doped areas 14 for serving as the source structures alter apparently due to the extensions and encroachments of the field oxide layer, and the operation performances of the trench power MOS devices decrease mainly due to the encroachment area. Generally, the encroachment areas A extend about 400 angstroms when the field oxide layer 16 has a thickness about 2500 angstroms.
As described above, with the integration of the semiconductor process increasing, the scales of the various devices manufactured on the substrate become smaller and smaller. It is noted that the scales of the doped areas 14 and the trench structure 8 defined on the substrate 2 are also decreased substantially. Thus, the encroachment areas A make the yield decrease mainly and make the channel length shrink.